1. Field of the Invention
The present invention relates to a method of manufacturing a plasma display panel and to a plasma display apparatus, and more particularly to, for example, a method of manufacturing a plasma display panel and a method of manufacturing a plasma display apparatus wherein electrodes and a dielectric layer are formed in the same baking (calcining) step.
2. Description of the Related Art
In general, a plasma display apparatus having a plasma display panel as a main component (hereinafter, also referred to as “PDP”) has various advantages compared with a CRT (Cathode Ray Tube) display or liquid crystal display apparatus, or the like, in that it produces no flicker, has a larger display contrast ratio, greater capacity for providing a large screen in a thin unit, faster response, and the like. Therefore, in recent years, plasma display apparatus are used as large-size flat-screen television receivers, displays for information processing devices, and the like.
A plasma display apparatus displays images by irradiating ultraviolet light generated by discharge, onto a fluorescent body, and extracting the visible light generated thereby. Plasma display apparatus can be categorized broadly according to their operating scheme into AC type apparatus wherein the electrodes are covered with a dielectric body and operate indirectly in a state of alternating current discharge, and DC type apparatus wherein the electrodes are exposed to the discharge space and operate in a state of direct current discharge. AC type apparatus, in particular, yield high luminosity and allow large-screen displays to be achieved readily by means of a relatively simple structure, and hence they are used widely. AC type plasma display panels having different electrode structures, namely, surface discharge type panels and opposed electrode type panels, have been proposed.
In general terms, a plasma display panel which forms the main component of an AC type plasma display apparatus is constituted by positioning a front surface substrate made from a transparent material, such as glass, and a rear surface substrate, in an opposing fashion, and forming a discharge gas space for generating plasma between the two substrates.
An AC type plasma display apparatus equipped with a plasma display panel of a three-electrode surface discharge structure can suppress the effects of high-energy ions generated by the surface discharge conducted at the front surface substrate, and therefore can achieve long life. Thus, this type of AC type plasma display apparatus can be applied in the widest range of situations. In the three-electrode surface discharge structure, row type electrodes consisting of scanning electrodes and sustaining electrodes (common electrodes) are disposed in parallel to each other in the horizontal direction on the inner surface of the front surface substrate, which is one of the aforementioned pair of substrates forming discharge cells (hereinafter, called “cells”), and column electrodes consisting of address electrodes (data electrodes) are disposed vertically in a direction orthogonal to the row electrodes on the inner surface of the rear surface substrate which is the other of the pair of substrates.
In a three-electrode surface discharge type AC plasma display apparatus, a write discharge for selecting a discharge cell that is to be displayed (illuminated) is performed between an address electrode on the rear surface substrate and a scanning electrode on the front surface substrate. Then, a sustaining discharge (display discharge) based on a surface discharge in the selected cell is performed between a scanning electrode and a sustaining electrode on the front surface substrate. The scanning electrode and sustaining electrode form an electrode pair. In such a plasma display panel, red, green and blue fluorescent layers are formed on the inner surface of the rear surface substrate, in such a manner that a color plasma display apparatus capable of emitting light of multiple colors is provided.
As shown in FIG. 16 of the accompanying drawings, a plasma display panel 101 forming the principal component of a plasma display apparatus includes a front surface substrate 102 and a rear surface substrate 103 in an opposing fashion, and discharge gas spaces 104 formed between the front surface substrate 102 and the rear surface substrate 103.
The front surface substrate 102 includes a front surface glass substrate 105, scanning electrodes 106, sustaining electrodes 107, transparent dielectric layer 108 and protective layer 109. The front surface glass substrate 105 is made of a transparent material, such as glass. The scanning electrodes 106 and sustaining electrodes 107 include transparent electrodes 106a and 107a made of tin oxide, ITO (Indium Tin Oxide), or the like, formed in a parallel fashion in the row direction on the inner surface of the front surface glass substrate 105, and bus electrodes 106b and 107b made of Al, Cu, Ag, or the like, placed on the transparent electrodes 106a and 107a for reducing the resistance value. The transparent dielectric layer 108 is made of a low-melting-point glass, such as PbO (lead oxide), and covers the scanning electrodes 106 and the sustaining electrodes 107. The protective layer 109 is made of MgO (magnesium oxide), or the like, having a high secondary electron emission coefficient and excellent anti-sputtering properties, for the purpose of protecting the transparent dielectric layer 108 from the discharge generated during operation.
The rear surface substrate 105 includes a rear surface glass substrate 110, address electrodes 111, white dielectric layer 112, partitions 113 and fluorescent layers 114. The rear surface glass substrate 110 is made of a transparent material, such as glass. The address electrodes 111 are made of Al, Cu, Ag, or the like, and formed in parallel in the column direction on the inner surface of the rear surface glass substrate 110. The white dielectric layer 112 covers the address electrodes 111. The partitions 113 are made of low-melting-point glass, or the like. The partitions 113 extend in the vertical direction in order to maintain the discharge gas space 104 which is filled with a discharge gas, such as He (Helium), Ne (Neon), Xe (Xenon), in either independent or combined fashion, and to divide the space into individual discharge cells. The fluorescent layers 114 include red, green and blue fluorescent layers, and are disposed on the base portion and side portions of the discharge cell formed by the partitions 113, for converting the ultraviolet light generated by the electrical discharge of the discharge gas into visible light.
For the red fluorescent material, (Y, Gd) BO: Eu, or (Y, GD) BO3: Eu is used, for the green fluorescent material, Zn2SiO4: Mn is used, and for the blue fluorescent material, BaMgAl10O17: Eu is used.
A method of manufacturing a three-electrode surface discharge type AC plasma display panel 101 of this kind will now be described with reference to FIG. 16 and FIG. 17 of the accompanying drawings. FIG. 17 depicts the flowchart of the manufacturing process.
Firstly, as shown in FIG. 16, transparent electrodes 106a and 107a are formed in parallel in the horizontal direction H on the inner surface of the front surface glass substrate 105, thereby forming the front surface substrate 102 (step SA11 (FIG. 17)).
Then, bus electrodes 106b and 107b for reducing the resistance are formed in the horizontal direction on top of the transparent elements 106a and 107a (on the lower surface thereof in FIG. 16) (step SA12). More specifically, if silver is chosen as the electrode material, the bus electrodes 106b and 107b are formed by patterning a silver paste consisting of powdered silver, glass frit and an organic binder, by means of screen printing or the like, burning away the organic binder and softening the glass frit by baking (calcining) the silver paste, and fixing a bus electrode pattern to the front surface glass substrate 105.
In this way, scanning electrodes 106 and sustaining electrodes 107 are formed by means of the transparent electrodes 106a and 107a, and the bus electrodes 106b and 107b. 
Next, a transparent dielectric layer 108 covering the scanning electrodes 106 and the sustaining electrodes 107 is formed (step SA13). More specifically, the transparent dielectric layer 108 is formed by forming a glass paste consisting of glass frit and an organic binder, by means of screen printing or a table coater, or the like, then burning away the organic binder and softening the glass frit by baking the glass paste, and fixing a transparent dielectric layer pattern to the front surface glass substrate 105.
Next, a protective film 109 for protecting the transparent dielectric layer 108 from discharges is formed (step SA14). Thus, the front surface substrate 102 is completed.
As shown in FIG. 16, in order to manufacture the rear surface substrate 103, address electrodes 111 are formed in parallel in the vertical direction on the upper surface of the rear surface glass substrate 110 (step SB11 (FIG. 17)). More specifically, if silver is selected as the electrode material, address electrodes 111 are formed by patterning a silver paste consisting of powdered silver, glass frit and an organic binder, by means of screen printing, or the like, then burning away the organic binder and softening the glass frit by baking the silver paste, and fixing an address electrode pattern to the rear surface glass substrate 110.
Next, a white dielectric layer 112 covering the address electrodes 111 is formed (step SB12). More specifically, the white dielectric layer 112 is provided by forming a glass paste consisting of glass frit and an organic binder by means of screen printing, a table coater, or the like, then, burning away the organic binder and softening the glass frit by baking the glass paste, and fixing a white dielectric layer pattern to the rear surface glass substrate 110.
In order to demarcate the discharge cells, partitions 113 are formed on the white dielectric layer 112 in a stripe fashion (step SB13). More specifically, partitions 113 are formed by coating a glass paste consisting of glass frit and an organic binder uniformly on the white dielectric layer 112 by reverse coating, slit coating, or the like, then patterning a resist thereon, cutting openings in the resist by sandblasting, or the like, and baking the glass paste, thereby burning away the organic binder and softening the glass frit, and causing a partition pattern to become fixed to the white dielectric layer 112.
Next, fluorescent layers 114 are formed between the respective partitions 113 (step SB14).
Then, sealing frit is coated about the outer perimeter portion of the rear surface glass substrate 110 and this frit is baked, thereby completing the rear surface substrate 103 (step SB15).
Then, the front surface substrate 102 and the rear surface substrate 103 are placed in an opposed state, separated from each other by a gap of approximately 100 μm therebetween. In this state, the substrates 102 and 103 are bonded together in such a manner that the extending direction of the electrode pairs (row direction) is orthogonal to the extending direction of the address electrodes 111 (column direction), and in such a manner that a discharge gas space 104 is formed between the substrates 102 and 103 (step SC16). The perimeter portion of the substrates 102 and 103 is then sealed hermetically by means of a sealing material made of frit glass, for example (step SC17).
After the frit glass is coated on the perimeter section of the rear surface substrate 103, the front surface substrate 102 and the rear surface substrate 103 are baked in the bonded state, so as to melt the frit glass and join the front surface substrate 102 to the rear surface substrate 103 in the form of a panel. The discharge cells are demarcated by the partitions 113.
Next, the front surface substrate 102 and the rear surface substrate 103 forming a panel shape are introduced into a heating oven. An air pipe is connected to the discharge space formed between the front surface substrate 102 and the rear surface substrate 103, and the substrates are heated in vacuum conditions while expelling the air from the discharge space. Then, a discharge gas consisting of a mixed rare gas containing xenon, for example, is introduced into the discharge gas space 104 at a prescribed pressure, thereby filling the discharge gas space. The air pipe is then sealed by overheating thus closing off the open end of the pipe (step SC18). In this way, discharge gas is filled into the discharge gas space 104.
An electrical discharge is then generated inside the discharge cells and the discharge is continued for a prescribed period of time so that the discharge becomes stable (step SC19).
In this way, discharge gas is filled into the discharge gas space 104 and a plasma display panel 101 is completed.
As described above, it is necessary to perform a large number of baking steps in order to manufacture a plasma display panel 10. By means of these baking processes, the organic binder contained inside the paste layers is burnt away and no organic components are left remaining inside the panel, while at the same time, the electrode material and other materials become fixed to the glass substrates due to the softening of the glass components therein.
Next, a method of performing baking will be described in detail with reference to FIG. 18 of the accompanying drawings.
As shown in this diagram, the temperature profile of the baking process includes a temperature rise portion L1, a binder removing portion L2, another temperature rise portion L3, a temperature-keeping portion L4, and a temperature fall portion L5.
In the first temperature rise portion L1, from time t0 until time t1, the temperature is increased to a temperature Ta approximately 10-20° C. higher than the burning temperature of the organic binder. The rate of temperature rise is set to approximately 10-20° C. per minute.
In the binder removal portion L2, the temperature Ta (i.e., baking temperature) is maintained for a prescribed period of time (binder removal time) from time t1 to time t2, thereby causing the organic binder in the paste to burn away completely. This prescribed time period (t2−t1) is determined by taking account of the type of organic binder contained in the paste, and the respective thickness of the electrodes, transparent dielectric layer and white dielectric layer, amongst other factors. Generally, this time period is set to around 5-20 minutes.
In the second temperature rise portion L3, from time t2 until time t3, the temperature is raised to a temperature Tb equal to or exceeding the softening point of the glass frit.
The softening point is taken to be the temperature at which a sample of the glass frit transforms from a sintering shrinkage phase to a soft fluid phase due to temperature rise, in a Differential Thermal Analysis (DTA). In other words, the above mentioned softening point is as the DTA softening point in this specification.
In the temperature-keeping portion L4, the temperature Tb is maintained as a baking temperature for a prescribed time period (hold time) from time t3 until time t4. This hold time (t4−t3) is set to the time period required until the glass frit softens completely and until all air bubbles are removed entirely from the electrodes and dielectric layers. In general, this time period is approximately 10-40 minutes.
In the temperature fall portion L5, the temperature declines at a temperature decline rate generally set to approximately 3-7° C. per minute, from time t4 until time t5.
Normally, if a glass sheet is cooled rapidly, deformation or distortion will be left in the glass sheet due to uneven cooling, and hence the glass may fracture or suffer from uneven shrinkage upon baking. This fracturing or uneven shrinkage of the glass may be several hundred ppm in size, and in a 42-inch plasma display panel for example, the uneven shrinkage will be approximately several 100 μm. Considering that the cells emitting red, green and blue light in a 42-inch VGA class display apparatus are approximately 350 μm in size, this extent of deformation of the glass substrate caused by sudden cooling is a critical problem in plasma display apparatus. Therefore, in general, the temperature is lowered gradually in order to avoid residual distortion in the glass.
Consequently, in the case of a baking temperature of 600° C., for example, the time period required for one baking process is approximately 2 hours at shortest, and approximately 5 hours at longest. Under these conditions, in order to manufacture with a tact time of two minutes, the baking oven is required to have a length of 60-150 meters per baking operation, and it must have a width capable of accommodating a substrate of approximately one meter square. If a baking oven of this kind is required for each of the baking processes illustrated in FIG. 17, then the installation surface area and power consumption required for the baking oven will be huge, the building accommodating the plasma display apparatus mass-production plant will inevitably be very large, energy consumption will be huge, and the manufacturing costs will also be very high.
In order to reduce the time required in the baking processes, technology has been proposed wherein an electrode pattern is formed on a substrate by using a conductive ink containing a conductive powder and an organic binder that can be removed by baking, a dielectric layer pattern is then formed so as to cover the electrode pattern by using a dielectric forming paste containing glass frit and an organic binder that can be removed by baking, and an electrode layer and a dielectric layer are then formed by baking the electrode pattern and the dielectric layer pattern simultaneously (see, for example, Japanese Patent Application Laid-open (Kokai) No. 2001-297691).
In this technique, a partition pattern is formed on the dielectric layer pattern by using a partition forming paste containing glass frit and an organic binder, and the electrode layer, the dielectric layer and the partitions are formed by simultaneously baking the electrode pattern, the dielectric layer pattern and the partition pattern. An under-layer pattern is formed on the substrate by using an under-layer forming paste containing glass frit and an organic binder, an electrode pattern is formed on top of the under-layer pattern, and a dielectric layer pattern is formed on top of the electrode pattern. Then, an under-layer, an electrode layer and a dielectric layer are formed by simultaneously baking the under-layer pattern, the electrode pattern and the dielectric layer pattern.
Technology has also been proposed wherein a metal paste layer containing powdered metal and glass frit is formed on a substrate, and a glass paste layer containing glass frit is formed on top of the metal paste layer, then an electrode layer containing crystallized glass and a dielectric layer consisting of a low-melting-point glass layer are formed by simultaneously baking the metal baste and the glass paste (see Japanese Patent Application Laid-open No. 2003-223851, for example).
Here, simultaneous baking is performed so that the peak of crystallization temperature of the crystallized glass has a value lower than the softening point of the low-melting-point glass (the abovementioned DTA softening point).
In the technology disclosed in Japanese Patent Application Laid-open No. 2001-297691, in particular, the powdered silver, or the like, forming the conductive powder is dispersed into the dielectric medium during the simultaneous baking process, thus causing the dielectric medium to assume a yellow color. If this simultaneously baked substrate is used as a front surface substrate, then the display quality of the resulting plasma display apparatus is degraded markedly.
More specifically, if two or more paste layers are baked simultaneously, then the components in the different layers may move and become mixed together, and air bubbles may occur within the layers. In particular, if silver is used as the conductive material, then the silver will disperse into the dielectric medium regardless of the presence or absence of glass frit in the conductive ink, and hence the transparent dielectric layer will turn yellow.
In the technology disclosed in Japanese Patent Application Laid-open No. 2001-297691 and Japanese Patent Application Laid-open No. 2003-223851, the electrode layer becomes conductive after baking has been performed. Therefore, even if faults in the electrodes are identified by performing an electrical inspection, or the like, after baking, it is not possible to repair these faults since the respective layers are baked simultaneously and most of the electrode layer is already covered with the dielectric layer. Thus, defective products may result.
More specifically, an electrode layer formed by a thick film technique, such as screen printing, offset printing, photosensitive paste coating, or the like, using silver, or the like, as a conductive material, only becomes conductive when the organic binder is removed by baking. If simultaneous baking is not adopted, then the electrodes are usually inspected after baking by means of image inspection using image recognition, and electrical inspection wherein current is actually passed through the electrodes and any connection failures or shorting to adjacent electrodes are identified. Any faults can be repaired if abnormalities are discovered as a result of these inspection processes. However, if simultaneous baking is adopted, it is not possible to repair the electrode layer, since a dielectric layer will already be formed thereon.
In the technology disclosed in Japanese Patent Application Laid-open No. 2001-297691, in particular, if the simultaneous baking process is conducted, gas is generated during baking upon burning away of the organic binder contained in the electrode pattern and this gas escapes into the dielectric layer covering the electrode layer. Since the gas cannot pass through the dielectric layer, it forms bubbles which become trapped inside the dielectric layer. This can give rise to voltage resistance faults in the dielectric layer when the display panel is used.
In the technology disclosed in Japanese Patent Application Laid-open No. 2003-223851, in particular, although the problems of the dispersion of silver, or the like, into the dielectric layer and the generation of gas bubbles are resolved, the type of glass frit that can be used in the metal paste is restricted to crystalline glass, for example.